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Solving Quantified Boolean Formulas with Circuit Observability Don't Cares

机译:用电路可观察性解决量化的布尔公式不关心

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Traditionally the propositional part of a Quantified Boolean Formula (QBF) instance has been represented using a conjunctive normal form (CNF). As with propositional satisfiability (SAT), this is motivated by the efficiency of this data structure. However, in many cases, part of or the entire propositional part of a QBF instance can often be represented as a combinational logic circuit. In a logic circuit, the limited observability of the internal signals at the circuit outputs may make their assignments irrelevant for specific assignments of values to other signals in the circuit. This circuit observability don't care (ODC) information has been used to advantage in circuit based SAT solvers. A CNF encoding of the circuit, however, does not capture the signal direction and this limited observability, and thus cannot directly take advantage of this. However, recently it has been shown that this don't care information can be encoded in the CNF description and taken advantage of in a DPLL based SAT solver by modifying the decision heuristics/Boolean constraint propagation/conflict-driven-learning to account for these don't cares. Thus far, however, the use of these don't cares in the CNF encoding has not been explored for QBF solvers. In this paper, we examine how this can be done for QBF solvers as well as evaluate its practical benefits through experimentation. We have developed and implemented the usage of circuit ODCs in various parts of the DPLL-based procedure of the Quaffle QBF solver. We show that DPLL search based QBF solvers can use circuit ODC information to detect satisfying branches earlier during search and make satisfiability directed learning more effective. Our experiments demonstrate that significant performance gain can be obtained by considering circuit ODCs in checking the satisfiability of QBFs.
机译:传统上,定向的布尔式(QBF)实例的命题部分已经使用联合正常形式(CNF)表示。与命题可靠性(SAT)一样,这是通过该数据结构的效率的激励。然而,在许多情况下,QBF实例的部分或整个命题部分通常可以表示为组合逻辑电路。在逻辑电路中,电路输出处的内部信号的有限可观察性可以使其分配对电路中的其他信号的特定分配不相关。该电路可观察性不关心(ODC)信息已被用于优于基于电路的SAT溶剂。然而,电路的CNF编码不会捕获信号方向和这种有限的可观察性,因此不能直接利用该信号方向。然而,最近已经表明,通过修改决策启发式/布尔约束传播/冲突驱动的学习来解释这些不在CNF描述中,可以在CNF描述中进行编码,并利用在基于DPLL的SAT求解器中的优势。不要关心。然而,到目前为止,QBF求解器尚未探索使用这些不关心CNF编码。在本文中,我们研究了如何为QBF求解器进行这一点,并通过实验评估其实际效益。我们已经开发并实施了电路ODC在QBF解算器的基于DPLL的过程的各个部分中的使用。我们表明基于DPLL搜索的QBF求解器可以使用电路ODC信息在搜索期间先前检测满足分支,并使得可取性的定向学习更有效。我们的实验表明,通过考虑电路ODC检查QBFS的可靠性时,可以获得显着的性能增益。

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