首页> 外文会议>IEEE International Conference on Software Engineering and Formal Methods >Specifying and Checking Refinement Relationships in VDM++
【24h】

Specifying and Checking Refinement Relationships in VDM++

机译:在VDM ++中指定和检查细化关系

获取原文

摘要

Formal methods allow to verify several properties of specifications and implementations. Intra-specification consistency means that a specification does not contradict itself. When specifications evolve over time, one also wants to check inter-specification consistencies, which mean that specifications defined earlier in the development cycle also hold at a later point in time. VDM++ is a popular and easy-to-use formal specification language. It uses testing instead of formal proofs to validate the consistency of specifications. The strictness of validations thus depends on the completeness of the corresponding test suites. Unfortunately, VDM++ does not support the verification of inter-specification consistencies. We define VDM-R, an extension of VDM++, which allows to annotate relationships between specifications. We also provide the tool VR2EvtB to translate from VDM-R to Event-B. Using an Event-B verifier, we can then formally validate intra- and inter-specification consistencies in an almost fully-automated process.
机译:正式方法允许验证规范和实现的几个属性。内部规范的一致性意味着规范并不矛盾。当规范随着时间的推移而发展时,人们也希望检查规范间的一致性,这意味着在开发周期中之前定义的规格也在稍后的时间点。 VDM ++是一种流行且易于使用的正式规范语言。它使用测试而不是正式证明来验证规范的一致性。因此,验证的严格性取决于相应的测试套件的完整性。不幸的是,VDM ++不支持验证规范间常量。我们定义VDM-R,vdm ++的扩展,这允许注释规范之间的关系。我们还提供工具VR2EVTB将VDM-R转换为事件-b。然后,我们可以在几乎完全自动化的过程中正式验证帧内和互总频繁的频率。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号