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The Intelligent Universal Virtual Laboratory (UVL)

机译:智能通用虚拟实验室(UVL)

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The objective of this project was to create a realistic, real-time, electrical engineering virtual laboratory. This project targets individuals who do not have adequate mobility of their upper bodies to perform laboratory experiments. To provide a more realistic and enhanced learning experience, the users of the virtual laboratory are allowed the freedom to build and test a wide variety of realistic electrical circuits, and be able to perform curriculum-based experiments. The main goal is to create an environment similar to a real electrical engineering laboratory, and to offer the user a way to learn the different aspects of instrumentation and circuitry.
机译:该项目的目标是创造一个现实,实时电气工程虚拟实验室。该项目针对没有足够的上半身流动的个人进行实验室实验。为了提供更现实和增强的学习体验,虚拟实验室的用户允许自由地建立和测试各种现实电路,并且能够执行基于课程的实验。主要目标是创造一个类似于真实电气工程实验室的环境,并为用户提供学习仪器和电路的不同方面的方法。

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