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Ultra Low Power Application Specific Instruction-Set Processor Design for a Cardiac Beat Detector Algorithm

机译:超低功耗应用特定指令集处理器设计用于心脏拍频算法

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High efficiency and low power consumption are among the main topics in embedded systems today. For complex applications, off-the-shelf processor cores might not provide the desired goals in terms of power consumption. By optimizing the processor for the application, one can improve the computing power by introducing special purpose hardware units. In this paper, we present a case study with a possible design methodology for an ultra low power application specific instruction-set processor. A cardiac beat detector algorithm based on the Continuous Wavelet Transform is implemented in the C language. This application is further optimized using several software power optimization techniques. The resulting application is mapped on a basic processor architecture provided by Target Compiler Technologies, and the processor is further optimized for ultra low power consumption by applying application specific hardware, and by using several hardware optimization techniques. The optimized processor is compared with the unoptimized version, resulting in a 55% reduction in power consumption. The reduction in the total execution cycle count is 81%. Power gating, and dynamic voltage and frequency scaling, are investigated for further power optimization. For a given case, the reduction in the already optimized power consumption is estimated to be 62% and 35%, respectively.
机译:高效率和低功耗是今天嵌入式系统的主要主题之一。对于复杂的应用,现成的处理器核心可能无法在功耗方面提供所需的目标。通过优化应用程序的处理器,可以通过引入特殊用途硬件单元来改善计算能力。在本文中,我们提出了一种案例研究,具有用于超低功耗专用指令集处理器的可能的设计方法。基于连续小波变换的心脏拍探测器算法在C语言中实现。使用多个软件功率优化技术进一步优化该应用。由此产生的应用程序映射到目标编译器技术提供的基本处理器架构,并且通过应用特定应用的硬件以及使用多个硬件优化技术,进一步优化了处理器以进行优化以进行超低功耗。优化的处理器与未优化的版本进行比较,导致功耗降低了55%。总执行周期计数的减少为81%。研究功率门控和动态电压和频率缩放,以进行进一步的功率优化。对于特定情况,已经优化的功耗的减少估计分别为62%和35%。

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