Prospects for Building Cortex-Scale CMOL/CMOS Circuits: A Design Space Exploration

摘要

In this paper, we briefly present a hardware design space exploration methodology to investigate various architectures/designs, and their relative performance/price tradeoffs. Using this methodology, we investigate CMOS and hybrid nano-scale (CMOL) based digital and mixed-signal circuits that implement Bayesian Memory (a simplified computational model based on George and Hawkins' model of the visual cortex, and Pearl's belief propagation), and for a cortex-scale spiking neural model. We then present the results of the hardware design space exploration, for implementing large-scale neuro/cortex inspired systems, and provide ballpark performance/price and scaling estimates for the same. These results provide some insight into the prospects for building large-scale Bayesian Inference engines, and neuromorphic networks using emerging nanoelectronics and/or nanogrid circuit structures. In general, the study of such hypothetical architectures will help guide research trends in intelligent computing (including neuro/cognitive systems), and the use of radical new device and circuit technology in these systems.