Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout

摘要

5 ultra low power / low energy static flip-flops operating in the subthreshold region are compared. They are a PowerPC603 flip-flop, a CMOS flip-flop, a nand2-based flip-flop and two minority-3 based flip-flops. Simulations based on netlists extracted from layouts, in a standard 65 nm CMOS process, include mismatch- and process-, voltage- and temperature (PVT-) variations. The flip-flops have regularity in layouts, for robustness against PVT variations, and are designed for a supply voltage of 250 mV. Comparisons for the same supply voltage indicate that the PowerPC 603 flip-flop has relatively low delay, the lowest power consumption and PDP, and close to average standard deviation in the delay, among the 5. The CMOS variant has the lowest delay, relatively low power consumption and PDP. However, it has the largest relative standard deviation for delay. The minority-3 based flip-flops have the lowest relative standard deviation in delay, making them the most robust towards variations, in this sense. However, they have the largest delays, and highest power consumption and PDP figures, and have a significantly higher transistor count.