Mobility enhancement through substrate engineering

摘要

This article reviews various approaches being currently investigated to improve carrier mobility, including process induced strain, crystal and channel orientation optimization, and global strain. We first provide a synthesis of new generation (i.e. gate length from 90nm down to 30nm) device performance in term of Ids, and we discuss the efficiency of each mobility enhancement method for both PMOS and NMOS devices. Then, after a brief overview on process induced strain, we mainly focus on the global approaches that require substrate engineering. For each of them, we present and explain the theoretical principle, the substrate fabrication and related challenges, including specific characterization, to finally summarize their impacts on device performance. A specific attention is placed on two global strain approaches, Strained Silicon on relaxed Silicon Germanium on Oxide (SGOI) and Strained Silicon on Oxide (SSOI). We present partially depleted device results on both substrates, demonstrating performance enhancement down to 40nm gate length devices. Finally, this paper concludes by presenting for the first time engineered substrates that combine orientation optimization and global strain approaches.