首页> 外文会议>Electrochemical Society Meeting >TOWARDS 0.5 nm EOT SCALING OF HfO_2/METAL ELECTRODE GATE STACKS
【24h】

TOWARDS 0.5 nm EOT SCALING OF HfO_2/METAL ELECTRODE GATE STACKS

机译:朝向0.5nm的HFO_2 /金属电极栅极堆叠的EOT缩放

获取原文

摘要

This paper presents results demonstrating the combination of a scaled HF-last/NH3 anneal bottom interface, scaled HfO2 high-k dielectric, and metal gate electrode to create gate stacks having an equivalent oxide thickness of 0.51 nm after a 1000C/IOS anneal. Transistors using this gate stack show gate current density two decades below that projected for a SiO2 transistor of similar EOT and good transistor characteristics. These results demonstrate that the use of HfO2 / metal gate transistors in this EOT regime will require changes in process, characterization, design, and reliability methodologies in order to successfully implement these structures into the semiconductor roadmap.
机译:本文介绍了缩放HF-LAST / NH3退火底界面,缩放的HFO2高k电介质和金属栅电极的组合,以在100℃/ iOS退火后产生氧化物厚度为0.51nm的浇口堆叠。使用该栅极堆叠的晶体管显示出于类似EOT和良好晶体管特性的SiO2晶体管投射的栅极电流密度二十年。这些结果表明,在该EOT方案中使用HFO2 /金属栅极晶体管将需要过程,表征,设计和可靠性方法的变化,以便成功地将这些结构实现成半导体路线图。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号