ALD HfSiO HIGH-K DIELECTRIC AND CVD-TaN METAL GATE

摘要

HfSiO gate dielectric grown by atomic layer deposition (ALD) method were demonstrated to fabricate dynamic random access memory (DRAM) devices. Easy control of the ratio of Hf to Si in HfSiO films and film thickness were observed. Due to DRAM process with higher thermal budget compared to logic process, a half-order of leakage current density was found to be higher at the same EOT from HfSiO MOS capacitors. Furthermore, TaN gate electrode deposited by chemical vapor deposition (CVD) was evaluated as a metal gate of HfSiO gate dielectric in logic transistors. The workfunction of TaN was found to be around midgap (4.6～4.7eV).