INTEGRATION OF HIMOS~(TM) FLASH MEMORY IN A 90NM CMOS TECHNOLOGY

摘要

The integration of a HIMOS? Flash memory array in a 90nm CMOS technology requires the addition of different modules. On top of CMOS technology with Cu interconnects, only 3 extra masks are needed. The HIMOS cell is a double poly split gate cell using both positive and negative voltages at the gate (9V/-6V) and 3.3V at the drain for programming and erasing. Therefore both high and medium voltage transistors are necessary in the periphery of the array. Together with the tunnel oxide of the cell and the digital gate oxide, this leads to the integration of 4 gate oxides on two poly levels. Patterning these double poly structures requires special attention: clearing high topography transitions in combination with tight CD control for digital transistors. Furthermore the integration of a high-k layer as interpoly dielectric is investigated as a route for scaling towards 45nm.