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机译:晶体管中的最先进

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摘要

MOS transistor scaling continues to be the key enabler for improving density and performance of microprocessors and other advanced logic products. The basic MOS scaling approach, namely reducing gate oxide thickness and gate length, is no longer adequate in itself to meet today's transistor performance and power requirements New materials, structures and techniques are being incorporated in advanced logic technologies to meet a more demanding set of transistor requirements. This paper will describe transistor innovations incorporated in Intel's latest 90 nm and 65 mn generation logic technologies and discuss how circuit power limitations will change the way we scale transistors in the future.
机译:MOS晶体管缩放继续成为提高微处理器和其他先进逻辑产品的密度和性能的关键推动器。基本MOS缩放方法即降低栅极氧化物厚度和栅极长度,不再适用于本身,以满足今天的晶体管性能和电源要求,新材料,结构和技术正在进行到先进的逻辑技术中,以满足更苛刻的晶体管组要求。本文将描述在英特尔最新的90纳米和65名MNE代逻辑技术中的晶体管创新,并讨论了电路功率限制如何在未来扩展晶体管的方式改变。

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