In this paper, we propose an evolutionary method of synthesizing multiple-Valued (MV) arithmetic functions using Genetic Algorithms (GAs). The synthesis procedure is aimed at multi-level realization of the circuits subjected to the constraint set - 1) 100% functional completeness 2) minimum transistor count and 3) minimum number of levels in multi-level synthesis process. We encode the circuit using a chromosome with each chromosome represented in terms of a set of primary inputs and a set of gates from a pre-defined library. To arrive at a given circuit functionality, the length of the chromosome is increased if lower logic depths do not give 100% circuit functionality. Examples of evolved 4-valued half-adder, half-subtracter, 1-digit full adder and multiplier circuits are examined. The technique used in this paper gives novel as well as optimal synthesis solutions for MV logic circuits.
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