POWER AND AREA EFFICIENT WIRELINE ECHO CANCELLATION USING DIGIT-SERIAL CIRCUITS

摘要

Echo cancellation in high speed wire line systems such as Gigabit Ethernet is a much "faster" problem as compared to acoustic echo and is caused due to impedance mismatches. To counteract this problem, an echo canceller which is basically an adaptive linear filter is used. In this paper we investigate echo cancellation circuits that use digit-serial techniques and over-clocking to reduce area and power of the receiver architecture in wire line systems. The goal is to make the device parameterizable, achieving area and power minimization.