Area and power efficient echo cancellation for high-speed wire-line systems.

摘要

Echo interference is a major source of noise in many high-speed wire-line systems. This makes "echo cancellation" a crucial and important part of any transceiver. In this thesis, we present an echo cancellation unit for Gigabit Ethernet over copper, i.e., 1000BASE-T systems. The novelty of our design is its adaptive nature, meaning that the cancellation filter is designed to combat and respond differently to echoes of varying sizes.; Echo cancellation circuits in wire-line systems can be large and tend to dominate the area and power consumption of the receiver. In this thesis we address these issues by investigating circuits that use bit-serial techniques and over-clocking.; We performed FPGA and ASIC synthesis to obtain frequency, area and power characteristics. Results suggested that our circuits are applicable to 1000BASE-T systems. The results demonstrated that our cancellation filter would not add to receiver congestion, and would also keep the power consumption low.