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Behavioural Modelling Of Instrumentation Delta-Sigma ADC

机译:仪表仪表δ-Sigma ADC的行为建模

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摘要

This paper examines the quantization error of a modulator for delta-sigma analog-to-digital converter (DSADC). In opposite to many papers, the analytical equations are found in time domain. This approach allows the authors to present the modulator as analog-to-digital converter (ADC) of input signal to code for given length of digital sequences at the modulator output. Such presentation is useful for investigation of quantization error for ordinary DSADC and can also be considered as the base for a new ADC type. Both analytical equations and results of simulations are used to find the sources of quantization errors: effect of the scale end, limited number of code transition levels, unequal length of code bin widths, non-ideal digital filters. Some suggestions are made to decrease influence of mentioned sources on quantization error including the new ADC type with conversion delay.
机译:本文介绍了Delta-Sigma模数转换器(DSADC)调制器的量化误差。在与许多论文相反,分析方程位于时域中。该方法允许作者将调制器作为模数转换器(ADC)呈现为输入信号的用于代码,用于给定调制器输出的数字序列的长度。这种介绍对于普通DSADC的量化误差是有用的,并且也可以被认为是新ADC类型的基础。分析方程和模拟结果都用于找到量化误差的源:刻度结束的效果,码转换水平有限,代码箱宽度不等,非理想数字滤波器。一些建议是减少提到的来源对量化误差的影响,包括具有转换延迟的新ADC类型。

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