Design and Modelling of a High Resolution, Continuous-Time Delta-Sigma ADC: In-depth noise considerations and optimization

摘要

This work documents the important design considerations and high--level development of an efficient Continuous-Time DS A/D converter for given system requirements. Projecting characteristics is especially essential in the design of the option-versatile DS converter and involves both advanced control and signaling theory, in addition to circuit and system design. Thus, extensive simulations were carried out through synthesis and behavioral modelling.Synthesis was performed using R. Schreiers DS toolbox while modelling was done using the framework of Cadence with Virtuoso and Spectre. Behavioral modelling was based on the mixed-signaling language VerilogA. A list of candidates, meeting the performance requirements set, were formed from synthesis and two modulator architectures stood out; a multi-bit third order and a single-bit fifth order, both with an oversampling ratio of 32. Both feedback and feedforward loop filter structures were analyzed.A useful and powerful analysis was carried out to characterize and quantify the impact of location on nonidealities in DS modulators. The model was prepared for verification, helping to analyze, characterize and specify crucial parts of each structure. Decisive nonidealities, such as excess loop delay, finite DC gain, limited GBW, circuit noise and their influence on the overall modulator were included and examined. From this, a specification for the integrators as well as a preliminary noise and power budget was established.The final result ends in a realistic environment capable of analyzing different types of CTDS structures and making an informed decision on the most optimal and suitable configuration. Results from synthesis and behavioral modelling showed a great correspondance between the results obtained in each part. After an iterative process of evaluating performance among other metrics with nonideal effects, the best architecture was found to be the third order multi-bit feedback modulator, which achieved all of the requirements while consuming 3724uW