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CONTINUOUS-TIME DELTA-SIGMA ADC WITH SCALABLE SAMPLING RATES AND EXCESS LOOP DELAY COMPENSATION
CONTINUOUS-TIME DELTA-SIGMA ADC WITH SCALABLE SAMPLING RATES AND EXCESS LOOP DELAY COMPENSATION
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机译:连续时间的DELTA-SIGMA ADC,具有可缩放的采样速率和超大的环路延迟补偿
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摘要
Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.
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