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Analysis of a Multiplying DAC Employed for Synchronous Detection

机译:用于同步检测的乘法DAC分析

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Multiplying digital to analog converters can be used as synchronous detection circuits by combining a proper code sequence and an analog input at the reference. The output for a periodic signal has been derived under reasonable assumptions. The analysis shows that this type of synchronous detector is sensible only to harmonic components almost equal to a multiple of the number of samples per period. This result can be seen as a generalization of the classical two-level synchronous detection theory.
机译:将数字到模拟转换器乘以作为同步检测电路,通过组合相互参考的代码序列和模拟输入来用作同步检测电路。定期信号的输出已经在合理的假设下导出。该分析表明,这种类型的同步检测器仅灵活,仅对谐波分量几乎等于每个时段的样本数量的倍数。该结果可以被视为经典双层同步检测理论的概括。

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