FPGA MONTGOMERY MULTIPLIER ARCHITECTURES - A COMPARISON

摘要

Novel FPGA architectures for the SOS, CIOS and FIOS Montgomery multiplication algorithms are presented. The 18×18-bit multipliers and fast carry look-ahead logic embedded within the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions required by these algorithms. A detailed analysis is given, highlighting the advantages and weaknesses of each of these architectures when implemented in hardware. This shows that the CIOS multiplier architectures perform best overall, with the performance gap between this and the other options increasing as the word size used decreases. In addition, the SOS multipliers outperform the FIOS multipliers for larger word sizes, but vice versa as the word size decreases. It is also shown that one can tailor the multiplier architectures to be area efficient, time efficient or a mixture of both, by choosing a particular word size.