SRAM cell design protected from SEU upsets

摘要

There have been many solutions to create a soft error immune SRAM cell. These solutions can be broken down into three categories: a) hardening, b) recovery, c) protection. Hardening techniques insert circuitry in an SRAM cell possibly duplicating the number of transistors [1, 2]. Recovery techniques insert current monitors in SRAMs to detect SEUs and they employ error correcting codes or redundancy to mitigate these effects [3]. These techniques do not scale very well. Protection methods use capacitors in SRAM cells to absorb the excessive charge [5, 6, 7]. Although they provide sufficient protection, they affect adversely the write time. These models are effective against SEUs by maintaining the critical charge through extra capacitance. These models penalize the performance of the cells by increase the write time. We addressed the weakness of the write time by introducing a new design, SRAM-tct shown in Fig. 1, and we compare it to a standard 6-transistor SRAM as well as the SRAM-c cell with a capacitor introduced in [8]. We eliminated the influence of the additional capacitance on the write time, while increasing the SEU protection level. Our area overhead is comparable to other memory protection methods and recovery methods reported. Through experimental results we observed that the SRAM-tct model exhibited similar write time behavior as the regular SRAM cell with a minor penalty of 7percent.