High-bandwidth DRAM optimization

摘要

Memory bandwidth is a crucial part of digital light processing (DLP) projectors, switches, routers, and local WiFi boxes, so it requires the designer to consider many options. Dynamic random access memory (DRAM) enjoys an area advantage over static random access memory (SRAM) of 10 times or more, making it more cost-effective on a per-bit basis. However, for years, DRAM lagged behind SRAM in certain performance characteristics. This paper demonstrates that new DRAM devices not only match SRAM performance in key areas but exceed it in some parameters. This presentation's discussion focuses on recent advances in DRAM architecture with emphasis on reduced latency DRAM (RLDRAM~(TM)) technology. It provides an overview of the applicable memory device types, stressing the understanding of command bus and data bus utilization. To complement this understanding of command and data flows, graphical tools will be provided to enable selection of the optimal memory architecture for a given access pattern requirement. Optimization of different memory access patterns will also be discussed. The article will conclude with ideas on how to make designs flexible enough to support a range of performance and cost targets.