An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage

摘要

A technique to rapidly correct for DAC errors in the multi-bit first stage of an 11-bit pipelined ADC is presented. Using a split-ADC approach the digital background scheme is validated with a proof-of-concept prototype fabricated in 1.8V 0.18μm CMOS, where the calibration scheme improves the INL of the ADC at f{sub}s=45MS/s, from +6.1/-6.4LSB to +1.1/-1LSB after calibration. The SNDR/SFDR is improved from 46.9dB/48.9dB to 60.1dB/70dB after calibration. Calibration is achieved in ～10{sup}4 clock cycles.