首页> 外国专利> Pipelined ADC inter-stage error calibration

Pipelined ADC inter-stage error calibration

机译:流水线ADC级间误差校准

摘要

An analog-to-digital converter (ADC) is provided. The ADC includes a plurality of pipelined ADCs and an adjustment circuit. Each pipelined ADC is adapted to receive an analog input signal, has an adjustable transfer function, and includes a compensator. The adjustment circuit is coupled to each pipelined ADC to be able to adjust the transfer function for each pipelined ADC so as to generally eliminate an estimation ambiguity. Additionally, the adjustment circuit estimates an inter-stage error that includes at least one of an inter-stage gain error and a DAC gain error and adjusts the compensator for each pipelined ADC to compensate for the inter-stage error.
机译:提供了一个模数转换器(ADC)。 ADC包括多个流水线ADC和调节电路。每个流水线ADC适用于接收模拟输入信号,具有可调的传递函数,并包括一个补偿器。调整电路耦合到每个流水线ADC,从而能够调整每个流水线ADC的传递函数,从而大体上消除估计的歧义。另外,调节电路估计级间误差,该级间误差包括级间增益误差和DAC增益误差中的至少一个,并且针对每个流水线ADC调节补偿器以补偿级间误差。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号