A CPLD-Based Error-Correcting Decoder for Correcting Codes with Multi-Bit Errors

摘要

It is of practical significance to realize the error-correcting technology in digital signal transmission. In this paper we propose a new decoding method of coding by shortening code and full combination logic instead of using a lot of shifting registers as we do in the traditional error-correcting circuit, and use CPLD to realize this error-correcting decoder on that basis. CPLD has fast speed and large capability characteristics. In the support of EDA software, digital system can be easily designed by hardware description language (HDL). This error-correcting decoder adopts the ispMACH4000 family CPLD. In this paper, the work principle of this error-correcting decoder is first accounted and the function diagram of the CPLD-based error-correcting decoder is hereby given. We not only fully explain the function of encoding controller but also present some ABLE-HDL source codes. Practice proves that this error-correcting decoder possesses strong error-correcting ability, fast response speed and practicability.