A 3-D fast extractor for interconnect of multiple right-hand sides

摘要

With the development of VLSI circuits, the feature size has been decreased to the deep sub-micron level, and working frequency has reached 3GHz. IC performance depends directly on parasitic interconnect inductance and resistance. In this paper, we propose an improved filament refinement method based on Fast Multipole Method (FMM). An improvement of setting right-hand sides is proposed to accelerate the convergence rate of the iterative method in solving multiple right-hand sides (RHS). Experimental results show that the extractor presented here runs tens to hundred times faster than the FastHenry with comparable accuracy.