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Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates

机译：多基板三维集成电路中水平互连和电感的快速高频阻抗提取

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Chuan Xu; Navin Srivastava; Roberto Suaya; Senior Member; Kaustav Banerjee;
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年度 2014
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1. Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates [J] . Xu C., Srivastava N., Suaya R., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2012,第11期

机译：具有多个基板的3-D IC中的水平互连和电感器的快速高频阻抗提取
2. Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [J] . Srivastava N., Xu C., Suaya R., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2010,第5期

机译：对“存在多层导电基板时高频VLSI互连阻抗提取的解析表达式”的更正
3. Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate [J] . Srivastava N., Suaya R., Banerjee K. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2009,第7期

机译：多层导电基板存在下高频VLSI互连阻抗提取的解析表达式
4. Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate [C] . Srivastava, N., Suaya, R., Banerjee, K. Design, Automation & Test in Europe Conference & Exhibition;DATE 10 . 2010

机译：高效的3D高频阻抗提取，可用于分层基板上方的常规互连和电感器
5. High-frequency impedance extraction of interconnects considering substrate effects and exploration of single-walled carbon nanotubes for future VLSI interconnects. [D] . Srivastava, Navin. 2009

机译：考虑衬底效应的互连线的高频阻抗提取和用于未来VLSI互连线的单壁碳纳米管的探索。
6. Ultra-Small High-Frequency and Substrate-Immune Microtube Inductors Transformed from 2D to 3D [O] . Xin Yu, Wen Huang, Moyang Li, -1

机译：从2D转换为3D的超小型高频和基质免疫微管电感器
7. Accurate calculations of the high-frequency impedance matrix for VLSI interconnects and inductors above a multi-layer substrate: [O] . 2012

机译：对于多层基板上方的VLSI互连和电感器的高频阻抗矩阵的精确计算：

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates

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