The problem of test generation has been proved to be the NP-complete problem and it is becoming more and more difficult as the complexity of VLSI circuits and digital systems ever grows. Different techniques for solving the problem of test generation for digital circuits have been proposed over the years, for example, deterministic algorithm, simulation based algorithm and other algorithms. But there is no one that is far superior to the other algorithms; the test generation for digital circuits will remain a challenging problem for years to come. In this paper, a fuzzy test generation algorithm for combinational logic circuits is proposed. In our method, the fault value is represented as fuzzy logic value, and several key techniques are used to generate test vectors to achieve high fault coverage at low computational complexity. This new algorithm is composed of two phases. The first phase it generates the test vector by computing the fault value of the primary outputs, and computes it's fault-free value using the test vector to find the testable fault. In the second phase, it generates another test vector of the fault point by using the fault-free value of the fault point as constraint condition. This method is radically different from the conventional methods, and it doesn't need the process of backtracks. Some experimental results on the benchmark circuits demonstrate the feasibility of this algorithm.
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