A Design of the Interface between DSP and SDRAM

摘要

In this paper by use of Hardware Description Language (VHDL) and Complex Programmable Logic Device (CPLD), a design of the interface between TMS320VC33 and Synchronous DRAM (SDRAM) is accomplished, and expatiate the methods that solve the problems of access timing conversion and conflict between access and refresh in detail. Using this interface TMS320VC33 can access Dynamic RAM as easy as access Static RAM. The capacity of DSP system memory is improved greatly by use of this interface, and the need of DSP's application in data acquisition and image processing is met. Because this interface is designed by VHDL and CPLD, it can be modified easily to interface with other microprocessors or buses.