A Test Access Mechanism Interfacing with IEEE 1149.1 TAP for Testing IP Based System-on-a-Chip

摘要

The SoC (System-on-a-Chip) based on reusable embedded IP (Intellectual Property) introduces new challenges to the test, since the IP core user may not know the gate level implementation of the core, and the controllability and observability of the core that are limited by other cores and the user defined logic surrounding the core. These IP cores are usually embedded in chip deeply. This paper proposes a configurable TAM-Bus, a P1500 compliant Test Access Mechanism (TAM), and the TAM-Bus controller (TAM-controller) that is interfaced with JTAG at chip level. With P1500 wrapper, the SoC test architecture based on TAM-Bus is flexible, scalable and configurable. The paper also presents a novel interface to the chip level JTAG with that the IEEE 1149.1 (JTAG) Test Access Port (TAP) can be reused to provide control signals to the test components on chip. All IP cores' test can be controlled through the TAP under the control of the TAM-controller. The test architecture we presented has been implemented in an industry SoC. The test coverage remains 99.40%. The overhead increases only 0.17% due to TAM. The experiment results demonstrate that the test architecture can offer the solution for testing SoC.