Preliminary Study Towards the EMI-Induced Bit-Flips Prediction for COTS Microprocessors

摘要

The main thrust of this paper is to propose a general analysis involving conducted electromagnetic interference (EMI) at the processor power bus and the occurrence of bit-flips (soft-errors) in its memory elements. At the final end, we aim at accurately predicting EMI-induced bit-flips in commercial-off-the-shelf (COTS) microprocessors by means of pin-level fault injection. An in-depth experiment based on the MSP430F149-Texas Microcontroller has been carried out in order to understand the relationship between EMI-noise affecting processor power bus and the number of induced bit-flips in the processor memory elements. For this experiment, we have inspected the embedded RAM used to store application data as well as control state variables. This RAM also serves as stack area for the control part. The EMI consequences in terms of bit-flips have been considered for different levels of EMI. The set of EMI levels is defined according to the International Standard Normative IEC 61000-4-29, which rules test setup and test procedures for certificating DC-low power supplied electronics with respect to conducted EMI noise throughout its power-lines. For the proposed work, we have used a home-tailored Std. IEC 61000-4-29 test-compliance EMI generator to inject noise into the processor power lines. The obtained results are very promising and point towards a modeling to predict conducted EMI-induced bit-flips in processor memory elements.