This paper discusses the application of a new two-dimensional logarithmic number system (2DLNS) to the design of low-power processors for hearing-aid applications. The paper concentrates on the architecture of an optimized second base 8-band filterbank and an associated 16-bit binary to 2DLNS converter. The processor takes advantage of the low complexity, orthogonal nature, of the arithmetic used for multiplication and compression, and a simple binary converter. Details are provided for the filterbank processor including the description of a 0.18μm CMOS test chip recently submitted for fabrication.
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