Eliminating of the Drawback of Existing Testing Technique of Easily Testable PLAs Using An Improved Testing Algorithm With Product Line Rearrangement

摘要

An improved testing technique for easily testable programmable logic arrays (PLAs) is proposed that requires reduced testing time compared with existing techniques. It is demonstrated that the testing time actually increases for some PLAs using existing techniques, for simultaneous testing of PLAs, if the product lines of the PLAs are rearranged. However, the proposed technique does not suffer from this problem and the average testing time actually reduces even further if the product lines are sequenced in a given order, where existing techniques fail.