Timing Accurate Functional-Level Hardware Simulation with Pull Model Data Flow

摘要

Functional–level hardware simulation is a commonly used approach to validate various digital logic designs prior to fabrication. Discrete event simulation is particularly well suited for such modeling efforts, and is in widespread use throughout the computer architecture research community, as well as commercial entities that design and produce products based on digital logic. In prior work, we introduced a novel pull-model approach that resulted in a considerable improvement in execution time for these digital logic simulations. However, a significant shortcoming of our prior reported work using the pull-model was the lack of inclusion of timing delays between components in the model. The prior work assumed that any change in the output state of a component was immediately known to the corresponding inputs of directly connected devices. While this assumption is clearly unrealistic, such a model is still useful in determining the logical validity of digital designs, and allows quick–look analysis that the designs are logically correct. Here, we enhance the pull-model approach to include rise–time delays and speed-of-light delays in the component interconnects, and show that we still achieve considerable performance improvement over more traditional approaches. Additionally, we report performance results for several different test cases of varying sizes, and show performance improvements across the board.