A Pipelined Processor Suitable for A Bus-based Parallel Architecture

摘要

In this paper we introduce an efficient pipelined processor designed primarily for prototyping and analyzing a parallel system. The processor is intended for a bus-based parallel architecture with an interconnection based on dual of a hypercube. It can also be adapted for other parallel systems. The data path and control units of the pipelined processor are designed to efficiently fetch, decode, and execute each instruction. The pipeline consists of six stages: Fetch, Decode, Execute, Memory, Write Back, and Communication stages. The communication stage provides inter-processor communication between any processor and two other processors. We use an interrupt-driven communication approach. The pipeline includes several control units for data and control hazard detection and recovery to achieve a higher execution rate. The proposed pipelined is modeled and simulated in C language. We have developed a very user-friendly simulator for the processor. This high level simulator provides a very suitable environment for studying parallel systems.