A Visualization Framework for VHDL Analysis

摘要

We present a framework for visualizing structural and functional behavior in a HDL description. The intent is to assist designers in module reuse. Our approach is based on the perusal of the HDL code and employs signal and function analysis upon which new views of the module are based. A prototype software tool, VALET, which we are developing is described. While our tool is specifically targeted to VHDL descriptions, the overall approach can be adapted to alternative HDLs.