A design of a 3.5+1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance from loading the front stage circuit of the MDAC. A two-stage high gain and wide unity gain bandwidth op-amp is designed. Simulation by Hspice based on Chartered 0.18µ 1P5M CMOS process under 1.8V supply voltage shows −84.23dB THD of the input sampling switches, 114dB open-loop gain, 2.5GHz unity gain bandwidth of the op-amp, and 11-bit resolution settling of the output signal of the MDAC.
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