The application of CAE in mold flow of IC packaging has been developed for years. However, to predict EMC flow behavior accurately in IC packages during transfer molding is still a huge challenge due to its intrinsic limitations. In this paper, modeling technologies to analyze mold flow during semiconductor encapsulation have been developed. The leadframe separates the whole molding cavity into top and bottom cavities. Cavity thickness is the most important factor to the mold flow behavior. Unbalanced flow, due to large thickness difference between top and bottom cavities, causes air trapping and die pad tilt. Some packages which have larger thickness difference, such as 1 to 3 thickness-ratio TSOP, LOC-TSOP, DHS, EDHS and DPH Q-series packages, have a seriously unbalanced melt-front during molding. By observing the flow phenomenon from short-shot samples, it is found that the cavity thickness, bonding wire density, the size of leadframe openings, and surface roughness all affect EMC flow behavior. By considering these factors into the construction of a simulation model, numerical results show excellent agreement with actual experimental results for a DPH-LQFP package. The melt-fronts of numerical and experimental results are compared and shown. Further investigation to improve the package moldability was also studied. By using CAE software, molding defects can be easily detected and moldability problems can be improved efficiently to reduce manufacturing cost and design cycle time.
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