A High Definition H.264/AVC Hardware Video Decoder Core for Multimedia SoC's

摘要

H.264/MPEG-4 AVC is the latest coding standard jointly developed by the Video Coding Experts Group (VCEG) of ITU-T and the Moving Picture Experts Group (MPEG) of ISO/IEC. This paper describes an integrated application specific silicon hardware core which implements the H.264 standard at Main Profile with support for all broadcast formats up to and including high definition. The solution is highly optimized and consumes less than 160 milliwatts at 200 MHz for the decoding of high definition images at 30 frames per second when implemented on 130nm process. The implementation requires less than 300K gates and 24 MB of external system memory. Key features include a novel and innovative memory management scheme to reduce the bandwidth to the main system memory and an optimized single symbol per clock cycle CAB AC decoding engine.