A new Serial/parallel Architecture for a low power Modular Multiplier

摘要

A new architecture for a modular multiplier is introduced that allows the effi-cient implementation of a low-power crypto coprocessor for smartcards. The multiplier architecture is optimized for accelerating asymmetric cryptographic operations based on long integer modular arithmetic. A modular multiplication is performed in a serial/parallel manner, this means the multiplier is scheduled sequentially (bit by bit) and the multiplicand is scheduled fully parallel. The modular reduction operation is integrated within the multiplication by continued modulus subtraction. It is shown that the the serial/parallel architecture can be realized very easily in a full custom design methodology due to its high degree of regularity. For a 1024 bit modular multiplication the proposed multiplier requires about 1600 clock cycles, which allows to compute a 1024 bit RSA exponentiation in approx. 250 ms if the clock frequency is 10 MH_z.