Design and Realization of Memory High-level Synthesis

摘要

In this paper, the design and realization of memory high-level synthesis system is studied. We first establish the memory system with hierarchical structure based on Master-Slave Finite State Machine with Data-path (MSFSMD) model. The mapping algorithm converting array index to memory address is studied and adder-free mapping circuits are proposed. And last, a delay module for the requirements of memory access time and the communication between master and slave FSMD is also studied. It is proved that this memory architecture has the features of simple in realization, high speed of address conversion and flexible to generate different memory access delay. Moreover, the memory module (slave FSMD) is relatively independent to the master FSMD, so it is fit for reuse design and embedded ASIC system design.