An effective area router for CMOS analog cell circuits is proposed in this paper. It is based on a modified grid-less tile-expansion algorithm and corner stitching data structure. Compared with the existing routers that need pre-defined terminals before routing, our router decides the connecting positions of a net when routing the net. Such a strategy helps to reduce the length of the routing wires, which can not only save routing area, more importantly reduce the parasitic wire capacitance and resistance. Moreover the proposed router supports symmetry routing and makes use of semi-reserved layer model. The program has been successfully tested on different design examples.
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