THE 1-1-1-1 CASCADEDΣ-Δ MODULATOR

摘要

The techniques to design and fabricate a cascaded sigma-delta modulator composed of 4 1st-order sections is presented. By correcting the digital outputs with estimates of the parasitic errors due to analog circuit imperfections, uncancelled quantization noise terms can be removed. Specifically, compensation for the effects of amplifier finite gain and C-ratio mismatches allow for the realization of the 1-1-1-1 cascade. A 1-1-1-1 cascaded modulator, implemented as a fully differential switched-capacitor circuit, has been fabricated in a 1.2μm double-poly n-well CMOS process. Measurements of the modulator verify that for an amplifier gain of 60 dB, and C-Ratio mismatch errors of approximately 0.5%-1%, the error correction offers an overall improvement in SNDR of 12-23 dB. A 12-15 μV_(rms) sine wave can be restored with a positive SNDR for a sampling rate of 2.5 MHz and an OSR of 64.