With decreasing feature size on silicon, the coupling capacitances of buses grow rapidly causing a significant impact on the power consumption of the whole chip. Thus, buses should be designed and optimized to dissipate less power without sacrificing performance. In this paper, we address this problem by simultaneously optimizing wire permutation, inversion and spacing (space between consecutive wires) using a combination of optimal as well as genetic algorithms. Unlike previous studies, our approach is applicable to not only address buses (behave more regularly), but also instruction buses of microprocessors. For the spacing problem, an algorithm is presented which determines the optimal solution instead of applying time consuming heuristic algorithms as presented in [10]. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. We simulate different combinations among permutation, spacing, and inversion. Integrated all optimization techniques together, our approach can save energy up to 68% for the best case and 58% on average while only increasing the total wire space by about 50% (compared to a bus with minimal spacing between adjacent wires for a particular technology).
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