The 2.4F~2 Memory Cell Technology with Stacked-Surrounding Gate Transistor (S-SGT) DRAM

摘要

This paper reports that the Stacked-Surrounding Gate Transistor (S-SGT) DRAM achieves a cell size of 2.4F~2. The S-SGT DRAM is structured by stacking several SGT-type cells in series vertically. In order to realize cell size of 2.4F~2, we propose the cell design of S-SGT DRAM. By using proposed design, we demonstrate that the S-SGT DRAM can realize cell size of 2.4F~2 by process simulation, while cell size of conventional SGT DRAM is 4.8F~2. Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.