首页> 外文会议>IEEE International Solid-State Circuits Conference >64Mb 6.8ns Random ROW access DRAM macro for ASICs
【24h】

64Mb 6.8ns Random ROW access DRAM macro for ASICs

机译:64MB 6.8ns随机行访问ASICS的DRAM宏

获取原文

摘要

With the emerging huge demand for multimedia applications, even personal computers have come to require enhanced memory systems, especially for 3-D graphics, MPEG encoding, and image/ voice recognition. While the large memory bandwidth of RambusDRAMs and Synchronous DRAMs offers high-speed data transfer and large capacity, they fall short in terms of low latency. Despite the efforts made by many programmers to circumvent the effects of the high latency of DRAM access, memory access instructionscontinue to accumulate, which limit system performance. The many conditional branch/jump operations of mixed multi-media applications (e.g., MPEG-4), for example, make such attempts at circumvention almost completely impossible. In fact, both lower random access latency and larger bandwidth are actually more pressing requirements for the latest memory systems.
机译:随着对多媒体应用的巨大需求,即使是个人计算机也需要增强的内存系统,尤其是3-D图形,MPEG编码和图像/语音识别。虽然Rambusdrams和同步DRAM的大内存带宽提供高速数据传输和大容量,但它们在低延迟方面缩短。尽管许多程序员所做的努力,但是规避了DRAM访问的高延迟的影响,但内存访问指令联系累积的内存累积,限制了系统性能。例如,混合多媒体应用(例如,MPEG-4)的许多条件分支/跳跃操作,在规避中几乎完全不可能进行此类尝试。实际上,较低的随机接入延迟和较大的带宽实际上是对最新内存系统的更压低要求。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号