Applications of semiconductor test economics, and multisite testing to lower cost of test

摘要

This paper develops a Semiconductor Test Economic Model that can easily be applied to lowering overall cost of test and improving throughput. The "Model", designed to take the complexity out of Test Economics, describes all the variables that make up Cost Per Unit (CPU), and using managerial economic concepts, illustrates how they interact with each other, as well as the overall production goal of minimizing costs while maximizing throughput. This paper is written for Test Managers, Test Engineers, Product Engineers, and ATE Capital Equipment Buyers for the purpose of gaining insight analyzing test economics, in order to make better decisions on everyday Manufacturing issues related to: test time reduction, multisite testing, yield, handler indextime, ATE Utilization, and ATE purchasing.