An effective apparatus for at-speed self-testing

摘要

This paper presents a loop-based BIST scheme for at-speed testing. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed. Based on it, an approach to design and efficiently implement the proposed BIST scheme has been developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.