The frequency response of the individual components and their parasitic between those components dictate the ability of system to respond to the current demand from IC. The simplified PDN schematic, shown in Fig. 1, includes source, bypass capacitors, PCB P/G plane, PKG P/G plane and the on-chip decoupling capacitor. While analyzing the system power integrity (PI), it's used to extract the P/G plane models of PCB and PKG by commercial electric-magnet (EM) field Solvers, Sigrity/PowerSI is adopted in this paper, which used the physical design databases of the PKG and PCB, and the extracted models are proven accurate from many benchmarks and correlations. However, for the on-chip decoupling capacitor, it's a challenging to derive the detail information from IC vendors since those on-chip information are the commercial secrets. In this section, a methodology is proposed to extract the on-chip decoupling capacitance through some skills of testing and 3D EM modeling.
展开▼
机译：这些组件之间各个组件及其寄生的频率响应决定了系统响应IC的当前需求的能力。简化的PDN示意图如图2所示。如图1所示，包括源极，旁路电容器，PCB P / G平面，PKG P / G平面和片上解耦电容。在分析系统电源完整性（PI）的同时，它用于通过商用电磁 - 磁铁（EM）现场求解器提取PCB和PKG的P / G平面模型，在本文中采用SIGrity / PowerSi，它使用了物理设计数据库在PKG和PCB中，从许多基准和相关性被证明准确的提取模型。然而，对于片上解耦电容，从IC供应商派生的详细信息是一个具有挑战性，因为片上信息是商业秘密。在本节中，提出了一种方法来提取通过测试和3D EM建模的技能提取片上解耦电容。
展开▼
