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High Volume Manufacturing Ramp In 90nm Dual Stress Liner Technology

机译:90nm双应力衬垫技术的大容量制造坡道

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The ability to meet the demand for improved microprocessor performance is made difficult due to the simultaneous need not to increase power consumption. In order to meet these conflicting demands, IBM introduced a 90nm dual stress liner CMOS technology to improve performance without increasing power consumption. In IBM's 300mm fab, this technology was introduced on multiple microprocessors, designed by different design groups with different architectures. These microprocessors, which were originally designed for a single liner technology, were optimized for systematic yield, power/performance, circuit limited yield (CLY), and random defect limited yield. The benefit of the dual stress liner technology is demonstrated in the power/performance characteristic of a dual core microprocessor and the successful technology ramp is demonstrated by yields of two microprocessors.
机译:由于同时不需要增加功耗,使得满足改善微处理器性能的需求的能力。为了满足这些冲突的需求,IBM推出了一个90nm双应力衬里CMOS技术,以提高性能而不会增加功耗。在IBM的300mm Fab中,这项技术在多种微处理器上引入,由不同的设计组设计,具有不同的架构。这些微处理器最初设计用于单衬里技术,针对系统产量,功率/性能,电路有限的产量(CLY)和随机缺陷有限的产量进行了优化。双核微处理器的功率/性能特性证明了双核微处理器的功率/性能特性,并且通过两个微处理器的产量证明了成功的技术斜坡。

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