The paper proposes a new layout-driven multi-level logic factorization methodology for regular arrays of two-input cells, that can find practical applications in fine-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies. A new factorization algorithm for AND/OR/EXOR logic with multi-valued literals is introduced, that has application to minimization of Logic Cell Arrays, and improves on previous results. It is shown that an extended cube representation and efficient minimization rules can be used, that generalize the ESOP minimization approach. Results of program MINICT demonstrate big area savings for several functions.
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